Numerous types of consumer electronics products rely on some form of mass storage for retaining data or software for the execution of code by a microcontroller. Such consumer electronics are prolific, and include devices such as personal digital assistants (PDA's), portable music players, portable multimedia players (PMP's) and digital cameras. In PDA's, mass storage is required for storing applications and data, while portable music players and digital cameras require large amounts of mass storage for retaining music file data and/or image data. The mass storage solution for such portable electronics is preferably small in size, consumes minimal power, and has high storage density. This limits the selection to non-volatile forms of memory since volatile memories, such as static random access memory (SRAM) and dynamic random access memory (DRAM), require a constant application of power in order to retain data. As is known in the art, portable electronics rely on batteries that have a finite power supply. Therefore, non-volatile memories that retain data after power is removed are preferred.
While many consumer products use commodity Flash memory, Flash memory is indirectly used by consumers in products such as cell phones and devices with microprocessing functions. More specifically, the application specific integrated circuits (ASIC) commonly found in consumer electronics can have integrated Flash memory to enable firmware upgrades. Needless to say, Flash memory is versatile due to its optimal balance in size, storage density, and speed, making it a preferred non-volatile mass storage solution for consumer electronics.
FIG. 1 is a general block diagram of typical Flash memory of the prior art. Flash memory 10 includes logic circuitry for controlling various functions of the Flash circuits, registers for storing address and data, high voltage circuits for generating the required program and erase voltages, and core memory circuits for accessing the Flash memory array. The functions of the shown circuit blocks of Flash memory 10 should are well known in the art. Persons skilled in the art will understand that Flash memory 10 shown in FIG. 1 represents one possible Flash memory configuration among many possible configurations.
A read operation is a relatively straight-forward access of data stored at a particular memory location of the memory array, called an address. Prior to a write operation to a specific block of the memory array, the specific block must first be erased with the application of high voltages. A write operation, more accurately called a program operation, requires the careful application of high voltages to a selected memory location, followed by a program verify operation to ensure that the data has been properly programmed. Furthermore, since high voltages are used, the Flash chip must be designed to be relatively tolerant to inadvertent programming of non-selected memory cells.
FIGS. 2a, 2b and 2c are illustrations of the NAND memory cell string used in memory cell array 28. FIG. 2a is a circuit schematic of two NAND memory cell strings. FIG. 2b is a chip layout of the two NAND memory cell strings shown in FIG. 2a. FIG. 2c is a cross-sectional view of one NAND memory cell string shown in FIG. 2b along line A-A′. Each NAND memory cell string includes 32 serially connected floating gate memory cells 50 each connected to respective wordlines WL0 to WL31, a string select transistor 52 connected between the bitline 54 and the first floating gate memory cell 50, and a ground select transistor 56 connected between a common source line (CSL) 58 and the last floating gate memory cell 50. The gate of string select transistor 52 receives a string select signal SSL, while the gate of ground select transistor 56 receives a ground select signal GSL. The NAND memory cell strings share common wordlines, string select SSL, and ground select GSL signal lines. The construction and arrangement of the shown NAND memory string is well known in the art.
As previously mentioned, the NAND memory cell strings of the memory array are first erased, according to well known techniques in the art. Each block of NAND memory cell strings can be selectively erased, therefore one or more blocks can be simultaneously erased. When successfully erased, all erased floating gate memory cells 50 will have a negative threshold voltage. In effect, all erased memory cells 50 are set to a default logic state, such as a logic “1”, for example. Programmed memory cells 50 will have their threshold voltages changed to a positive threshold voltage, thus representing the opposite “0” logic state.
FIG. 3 shows a threshold voltage (Vt) distribution graph for erased memory cells and programmed memory cells. Due to process and voltage supply variations, the erased and programmed threshold voltages will be distributed within a voltage range. As shown in FIG. 3, erased memory cells can have a negative threshold voltage between −3V to −1V, while programmed memory cells can have a positive threshold voltage between 1V and 3V. Generally, a cell is programmed by applying a high voltage to its gate while keeping its source and drain terminals grounded. The high electrical field causes electrons in the memory cell channel to cross the gate oxide and embed in the floating gate (known as Fowler-Nordheim (F-N) Tunneling), thereby increasing the effective threshold voltage of the memory cell.
A brief discussion of how data is read from the NAND memory cell string now follows with reference to FIGS. 2a to 2c. To read data one memory cell 50, SSL and GSL are both set to a read voltage (Vread, typically higher than Vcc), of 5V for example, to turn on string select transistor 52 and ground select transistor 56. All wordlines except the wordline to be accessed are set to a read voltage (Vread), of 5V for example, while the wordline to be accessed is set to 0V. Therefore, all memory cells 50 having a threshold lower than 5V are turned on to couple the source and drain terminals of the selected memory cell having the 0V wordline, to the bitline 54 and the source line 58. If the selected memory cell is in the erased state (having a negative threshold voltage), it will turn on, thereby coupling the bitline 54 to the source line 58. On the other hand, if the selected memory cell in the programmed state (having a positive threshold voltage), it will not turn on, thereby isolating the bitline 54 from the source line 58. The presence or absence of current is then detected by sense amplifiers.
The aforementioned reading scheme will reliably access memory cell data if the erased and programmed threshold voltages remain within their respective ranges. However, the described situation is ideal and the threshold voltages of erased and programmed memory cells can potentially shift when memory cells are programmed.
Programming is typically done by the page, meaning that all the memory cells 50 in the block connected to the same wordline are selected to be programmed with write data (logic “0”) at the same time. The remaining memory cells are thus unselected during programming. Since the memory cells start in the erased state (logic “1”) prior to programming, only the memory cells to be programmed with the logic “0” should be subjected to the high electric fields necessary to promote F-N tunneling. However, due to the physical connections of the memory array, all the memory cells along the same wordline receive the same high voltage programming level. As a result, there is a potential that erased memory cells will have their threshold voltages unintentionally shifted. This is called program disturb, which is well known in the Flash memory field.
Therefore a program inhibit scheme is used for preventing those memory cells where no change from the erased state is required, from being programmed to the logic “0” state. There are two known program inhibit schemes that can be used. The first is a basic inhibit scheme and the second is a self-boosted inhibit scheme. Table 1 summarizes the voltages applied to the relevant signal lines of FIG. 2a for both schemes. It is assumed that all the memory cells 50 connected to WL27 are erased to the logic “1” state, and BL0=“0” and BL1=“1” data is to be written to the memory cells 50 accessed by wordline WL27.
TABLE 1Basic inhibitSelf-boosted inhibitBL00 V (VSS)0 V (VSS)BL1VPI (8 V for example)VCC (2.5 V for example)WL27VPGM (18 V for example)VPGM (18 V for example)WL0-WL26,VPASS (10 V for example)VPASS (10 V for example)WL28-31SSLVPASS (10 V for example)VCC (2.5 V for example),then 0 VGSL0 V (VSS)0 V (VSS)
For the basic inhibit scheme, VPGM is set to a sufficiently high program voltage to cause F-N tunneling with drain voltage of 0V on the selected cell. VPASS is set sufficiently high to render unselected cell transistors in the selected string conductive regardless of their programmed state, and to pass VPI to the memory cell where no programming is desired. At the same time, VPASS should be insufficiently high to initiate F-N tunneling on unselected cells. VPI is an inhibit voltage on BL1 set sufficiently high to inhibit F-N tunneling on the selected cell connected to WL27, since the voltage difference between VPGM and VPI in the channel of the memory cell connected to WL27 is now too small.
There are some problems with the basic inhibit scheme. VPI is provided by an internal high voltage generator during program operations, and a large capacity charge pump is required to supply VPI to the highly capacitive bitlines. This leads to a drastic increase in the power consumption and the chip size, which are both highly undesirable. Page buffers connected to the bitlines must now be configured for high voltage operation in order to provide VPI to the bitlines. High voltage transistors are larger than regular voltage transistors, which increase the page buffer size and consequently, the chip size. Programming speed is reduced due to the need to charge the highly capacitive bitlines to VPI, with the on-chip voltage generator which has a limited current supply.
The self-boosted inhibit scheme addresses the problems of the basic inhibit scheme. With the SSL transistors 52 turned on and the GSL transistors 56 turned off, 0V or ground voltage, is applied to bitline BL0, while a high voltage such as VCC is applied to bitline BL1. A 0V bitline (as in BL0) ties the channel of the associated NAND string to ground. When the program voltage VPGM is applied to the gate of the selected cell, the large potential difference between gate and channel results in F-N tunneling of electrons onto the floating gate, thereby programming the cell. In program inhibited cells, BL1 initially precharges the associated channels towards the VCC voltage. When the voltage of WL27 rises to VPGM, and the remaining wordlines reach VPASS, the series capacitances through the control gate, floating gate, channel, and bulk are coupled and the channel potential is automatically boosted.
This boosting occurs when the coupled channel voltage rises to Vcc-Vth (where Vth is the threshold voltage of the SSL transistor). At this point, the SSL transistor 52 turns off and the channel becomes a floating node. It has been calculated that the floating channel voltage rises to approximately 80% of the gate voltage, which is sufficiently high to prevent F-N tunneling from occurring.
However, program disturb can still occur. In particular, if VPASS is set to be too high, erased cells coupled to BL0 can be unintentionally soft programmed to the logic “0” state due to the relatively high difference in voltage between VPASS and the 0V channel. On the other hand, if VPASS is set to be too low, the erased memory cell connected to WL27 and coupled to BL1 may not receive sufficient channel boosting to inhibit F-N tunneling.
Unfortunately, with continued scaling down due to advances in semiconductor fabrication technology, the power supply VCC is also scaled to a lower level. This is disadvantageous for the self-boosted inhibit scheme. This is because the NAND cell string channel is initially precharged to Vcc-Vth of the SSL transistor 52 before self-boosting by VPGM and VPASS, and the boosted voltage is largely affected by the precharge voltage Vcc-Vth. Furthermore, to achieve higher packing density, designers are increasing the number of memory cells in each NAND string. Therefore, relative to a NAND string having 16 memory cells 50, the 32 memory cell NAND string shown in FIGS. 2a to 2c will endure twice as many program disturb cycles than a 16 memory cell NAND string.
Accordingly, the threshold of programmed and erased memory cells can be unintentionally shifted during programming operations. FIG. 4 shows threshold voltage (Vt) distribution graph for program disturbed erased memory cells and programmed memory cells. The solid curves correspond to the threshold distribution originally shown in FIG. 3, while the dashed curves show the shifted threshold distribution due to program disturb. This shifting can be due to accumulated number times a cell is disturbed, or a single program disturb event. This is very problematic as the shifted thresholds can affect read operations. As previously discussed for a read operation, the gate of a selected memory cell 50 is driven to 0V, while unselected memory cells receives a read voltage Vread at its gate, while unaccessed memory cells have their gates driven to a read voltage Vread. As shown in FIG. 4, the 0V level may not turn on those cells having threshold voltages shifted above 0V. Furthermore, unselected cells having their thresholds shifted over the Vread voltage will remain off, thereby isolating the accessed memory cell from its corresponding bitline.
One technique for minimizing program disturb is to reduce the voltage level of VPASS. This introduces an operational constraint on the Flash memory, whereby the memory cells of the NAND string must be programmed in a sequential pattern, starting from the memory cell farthest from the bitline. In this scheme, all memory cells in the NAND string between the memory cell being programmed (selected page) and the bitline contact must be in the erased state. Hence a lower VPASS voltage can be used for non-selected cells to ensure that the bitline voltage can be coupled to the selected memory cell in the NAND string. Unfortunately, no random page program operations can be executed, since programmed memory cells (having Vth higher than VPASS for example) between the selected memory cell and the bitline contact will impede the bitline voltage from reaching the selected memory cell. This random page program prohibition causes many restrictions and performance degradation in certain applications.
It is, therefore, desirable to provide a program inhibit scheme that minimizes program disturb in NAND Flash memory cells. More specifically, it is desirable to provide a program inhibit scheme where the VPASS voltage level can be reduced for minimizing program disturb in unselected memory cells where programming is undesired, while maximizing the boosted channel voltage of the selected memory cell where programming is undesired.